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Features
* EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and
2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for Altera(R) FLEX(R) and APEXTM FPGAs (Device Selection Guide Included) Available as a 3.3V (10%) and 5.0V (5% Commercial, 10% Industrial) Version In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX Devices, ORCA(R) FPGAs, Xilinx(R) XC3000, XC4000, XC5200, Spartan(R), VirtexTM FPGAs, Motorola MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Very Low-power CMOS EEPROM Process Programmable Reset Polarity Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible Across Product Family) Emulation of Atmel's AT24CXXX Serial EEPROMs Low-power Standby Mode High-reliability - Endurance: 100,000 Write Cycles - Data Retention: 90 Years for Industrial Parts (at 85C) and 190 Years for Commercial Parts (at 70C) Green (Pb/Halide-free/RoHS Compliant) Package Options Available
* * * *
* * * * * * *
FPGA Configuration EEPROM Memory AT17LV65A AT17LV128A AT17LV256A AT17LV512A AT17LV010A AT17LV002A 3.3V and 5V System Support
*
1. Description
The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17A series device is packaged in the 8-lead PDIP(1), 20-lead PLCC and 32-lead TQFP, see Table 1-1. The AT17A series configurator uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes.These devices also support a write-protection mechanism within its programming mode.
Note: 1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera's EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information.
The AT17A series configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.
Table 1-1.
AT17A Series Packages
AT17LV65A/ AT17LV128A/ AT17LV256A Yes Yes -
Package 8-lead PDIP 20-lead PLCC 32-lead TQFP
AT17LV512A Yes Yes -
AT17LV010A Yes Yes Yes
AT17LV002A - Yes Yes
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2. Pin Configuration
Figure 2-1. 8-lead PDIP
DATA DCLK (1) (WP ) RESET/OE nCS
1 2 3 4
8 7 6 5
VCC SER_EN (A2) nCASC(4) GND
Figure 2-2.
20-lead PLCC
NC DATA NC VCC NC 3 2 1 20 19 nCS GND NC (A2) nCASC(4) NC 9 10 11 12 13
DCLK (2) WP1 NC NC (1) (WP ) RESET/OE
4 5 6 7 8
18 17 16 15 14
SER_EN NC NC NC (READY(2)) NC
Figure 2-3.
32-lead TQFP
NC DATA NC NC NC VCC NC NC 32 31 30 29 28 27 26 25
NC DCLK NC (3) (WP1 ) NC NC NC RESET/OE NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
NC SER_EN NC NC READY NC NC NC
Notes:
1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. This pin is only available on AT17LV010A/002A devices. 4. The nCASC feature is not available on the AT17LV65A device.
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NC nCS NC GND NC NC (A2) nCASC NC
AT17LV65A/128A/256A/512A/002A
Figure 2-4. Block Diagram
SER_EN WP1(2) OSCILLATOR CONTROLL
OSCILLATOR
(3)
POWER ON RESET
DCLK READY
(2)
RESET/OE (1) (WP )
nCS
nCASC
Notes:
1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. The nCASC feature is not available on the AT17LV65A device.
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3. Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external controller. The configuration EEPROM's RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When RESET/OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17A series configurator. If nCS is held High after the RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS. When the configurator has driven out all of its data and nCASC is driven Low, the device tristates the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE.
4. Pin Description
AT17LV65A/ AT17LV128A/ AT17LV256A Name DATA DCLK WP1 I/O I/O I I I I 20 PLCC 2 4 - 8 9 10 O 12 A2 READY SER_EN VCC Note: I O I - 18 20 - 7 8 15 18 20 20 23 27 15 18 20 20 23 27 6 12 15 12 15 8 PDIP 1 2 - 3 4 5 AT17LV512A/ AT17LV010A 20 PLCC 2 4 5 8 9 10 32 TQFP 31 2 4 7 10 12
AT17LV002A 20 PLCC 2 4 5 8 9 10 32 TQFP 31 2 4 7 10 12
RESET/OE
nCS GND nCASC
1. The nCASC feature is not available on the AT17LV65A device.
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4.1 DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4.2
DCLK
Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the RESET/OE input is held High, the nCS input is held Low, and all configuration data has not been transferred to the target device (otherwise, as the master device, the DCLK pin drives Low).
4.3
WP1
WRITE PROTECT (1). This pin is used to protect portions of memory during programming, and it is disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. This pin is only available on AT17LV512A/010A/002A devices.
4.4
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low logic level resets the address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and must be programmed active High (RESET active Low) by the user during programming for Altera applications.
4.5
WP
Write protect (WP) input (when nCS is Low) during programming only (SER_EN Low). When WP is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the memory cannot be written. This pin is only available on AT17LV65A/128A/256A devices.
4.6
nCS
Chip Select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter and enables DATA to drive out. If the AT17A series is reset with nCS Low, the device initializes as the first (and master) device in a daisy-chain. If the AT17A series is reset with nCS High, the device initializes as a subsequent AT17A series device in the chain.
4.7
GND
Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended.
4.8
nCASC
Cascade Select Output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of one device is usually connected to the nCS input pin of the next device in the chain, which permits DCLK from the master configurator to clock data from a subsequent AT17A series device in the chain. This feature is not available on the AT17LV65A device.
4.9
A2
Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
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4.10
READY
Open collector reset state indicator. Driven Low during power-on reset cycle, released when power-up is complete. (recommended 4.7 k pull-up on this pin if used).
4.11
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC.
4.12
VCC
3.3V (10%) and 5.0V (5% Commercial, 10% Industrial) power supply pin.
5. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17A Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the Altera FLEX FPGA device interfaces
6. Control of Configuration
Most connections between the FPGA device and the AT17A Serial EEPROM are simple and self-explanatory. * The DATA output of the AT17A series configurator drives DIN of the FPGA devices. * The master FPGA DCLK output or external clock source drives the DCLK input of the AT17A series configurator. * The nCASC output of any AT17A series configurator drives the nCS input of the next configurator in a cascaded chain of EEPROMs. * SER_EN must be connected to VCC (except during ISP).
7. Cascading Serial Configuration EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the next clock signal to the configurator asserts its nCASC output low and disables its DATA line driver. The second configurator recognizes the low level on its nCS input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to a Low level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to a High level.
The AT17LV65A devices do not have the nCASC feature to perform cascaded configurations.
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8. AT17A Series Reset Polarity
The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms.
9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip.
10. Standby Mode
The AT17LV65A/128A/256A enters a low-power standby mode whenever nCS is asserted High. In this mode, the configurator consumes less than 50 A of current at 3.3V (100 A for the AT17LV512A/010A/002A). The output remains in a high-impedance state regardless of the state of the RESET/OE input.
11. Absolute Maximum Ratings*
Operating Temperature.................................... -40C to +85 C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
12. Operating Conditions
3.3V Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0C to +70C Supply voltage relative to GND -40C to +85C Min 3.0 3.0 Max 3.6 3.6 Min 4.75 4.5 5V Max 5.25 5.5 Units V V
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13. DC Characteristics
VCC = 3.3V 10%
AT17LV65A/ AT17LV128A/ AT17LV256A Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 100 100 150 A -10 2.4 Industrial 0.4 5 10 50 -10 0.4 5 10 100 -10 0.4 5 10 150 V mA A A Commercial 0.4 2.4 0.4 2.4 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 AT17LV512A/ AT17LV010A Min 2.0 0 2.4 Max VCC 0.8
AT17LV002A Min 2.0 0 2.4 Max VCC 0.8 Units V V V
14. DC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/ AT17LV128A/ AT17LV256A Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS1 Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 150 200 350 A -10 3.6 Industrial 0.37 10 10 75 -10 0.37 10 10 200 -10 0.37 10 10 350 V mA A A Commercial 0.32 3.76 0.32 3.76 0.32 V V Min 2.0 0 3.7 Max VCC 0.8 AT17LV512A/ AT17LV010A Min 2.0 0 3.86 Max VCC 0.8
AT17LV002A Min 2.0 0 3.86 Max VCC 0.8 Units V V V
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15. AC Waveforms
nCS
TSCE TSCE RESET/OE TLC DCLK TOE TCE DATA TOH TCAC TOH TDF THC THOE
THCE
16. AC Waveforms when Cascading
RESET/OE
nCS
DCLK TCDF DATA LAST BIT TOCK nCASL TOCE TOCE TOOE FIRST BIT
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17. AC Characteristics
VCC = 3.3V 10%
AT17LV65A/128A/256A Commercial Symbol TOE
(1)
AT17LV512A/010A/002A Commercial Min Max 50 55 55 0 55 50 25 25 30 0 25 15 25 25 35 0 25 10 0 50 Industrial Min Max 55 60 60 Units ns ns ns ns ns ns ns ns ns ns MHz
Industrial Min Max 55 60 80 0
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency
Min
Max 50 60 75
TCE(1) TCAC TOH TDF TLC THC TSCE THCE THOE FMAX
(2) (1)
0 55 25 25 35 0 25 10
25 25 60 0 25 10
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
18. AC Characteristics when Cascading
VCC = 3.3V 10%
AT17LV65A/128A/256A Commercial Symbol TCDF(2) TOCK(1) TOCE(1) TOOE(1) FMAX Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Input Clock Frequency 8 Min Max 60 55 55 40 8 Industrial Min Max 60 60 60 45 12.5 AT17LV512A/010A/002A Commercial Min Max 50 50 35 35 10 Industrial Min Max 50 55 40 35 Units ns ns ns ns MHz
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
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19. AC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/128A/256A Commercial Symbol TOE
(1)
AT17LV512A/010A/002A Commercial Min Max 30 45 50 0 50 50 20 20 20 0 20 15 20 20 25 0 20 15 0 50 Industrial Min Max 35 45 50 Units ns ns ns ns ns ns ns ns ns ns MHz
Industrial Min Max 35 45 55 0
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency
Min
Max 30 45 50
TCE(1) TCAC TOH TDF TLC THC TSCE THCE THOE FMAX
(2) (1)
0 50 20 20 35 0 20 12.5
20 20 40 0 20 12.5
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
20. AC Characteristics when Cascading
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65A/128A/256A Commercial Symbol TCDF(2) TOCK(1) TOCE(1) TOOE(1) FMAX Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay Maximum Input Clock Frequency 10 Min Max 50 35 35 30 10 Industrial Min Max 50 40 35 35 12.5 AT17LV512A/010A/002A Commercial Min Max 50 35 35 30 12.5 Industrial Min Max 50 40 35 30 Units ns ns ns ns MHz
Notes:
1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
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21. Thermal Resistance Coefficients(1)
Package Type 8P3 Plastic Dual Inline Package (PDIP) JC [C/W] JA [C/W] JC [C/W] JA [C/W](2) JC [C/W] JA [C/W](2) JC [C/W] JA [C/W](2) - - - - 15 50
(2)
AT17LV65A/ AT17LV128A/ AT17LV256A
AT17LV512A/ AT17LV010A 37 107
AT17LV002A
35 90
35 90
35 90
20J
Plastic Leaded Chip Carrier (PLCC) Thin Plastic Quad Flat Package (TQFP) Plastic Leaded Chip Carrier (PLCC)
32A
44J
Notes:
1. For more information refer to the "Thermal Characteristics of Atmel's Packages", available on the Atmel web site. 2. Airflow = 0 ft/min.
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22. Ordering Information
Figure 22-1. Ordering Code(1)
AT17LV65A-10PC
Voltage 3.3V Nominal to 5V Nominal
Size (Bits) 65 128 256 512 010 002 = 65K = 128K = 256K = 512K = 1M = 2M
Special Pinouts A = Altera
Package P J = 8P3 = 20J
Temperature C = Commercial I = Industrial U = Fully Green
Blank = Xilinx/Atmel/ Other
Q = 32A
Note:
1. The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the 8-lead package of Altera's EEPROMs, refer to the AT17LV65/128/256/512/010/002/040 datasheet available on the Atmel web site for more information.
Package Type 8P3 20J 32A 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
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22.1
Standard Package Options(1)
Memory Size Ordering Code AT17LV65A-10JC 64-Kbit(2)(7) AT17LV65A-10JI AT17LV128A-10JC 128-Kbit(7) AT17LV128A-10JI AT17LV256A-10JC 256-Kbit(3)(7) AT17LV256A-10JI AT17LV512A-10PC AT17LV512A-10JC AT17LV512A-10PI AT17LV512A-10JI AT17LV010A-10PC AT17LV010A-10JC AT17LV010A-10QC AT17LV010A-10PI AT17LV010A-10JI AT17LV010A-10QI AT17LV002A-10JC AT17LV002A-10QC AT17LV002A-10JI AT17LV002A-10QI 20J 8P3 20J 8P3 20J 8P3 20J 32A 8P3 20J 32A 20J 32A 20J 32A 20J 20J 20J 20J Package 20J Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
512-Kbit(4)(7)
1-Mbit(5)(7)
2-Mbit(6)(7)
22.2
Green Package Options (Pb/Halide-free/RoHS Compliant)(1)
Memory Size 512-Kbit(4)(7) 1-Mbit(5)(7) 2-Mbit(4)(7) Ordering Code AT17LV512A-10JU AT17LV010A-10JU AT17LV010A-10PU AT17LV002A-10JU Package 20J 20J 8P3 20J Operation Range Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C)
Notes:
1. Currently, there are two types of low-density configurators. The new version will be identified by a "B" after the datacode. The "B" version is fully backward-compatible with the original devices so existing customers will not be affected. The new parts no longer require a MUX for ISP. See programming specification for more details. 2. Use 64-Kbit density parts to replace Altera EPC1064. 3. Use 256-Kbit density parts to replace Altera EPC1213. 4. Use 512-Kbit density parts to replace Altera EPC1441. 5. Use 1-Mbit density parts to replace Altera EPC1 6. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT17LV002A devices do not support JTAG programming; Atmel AT17LV002A devices use a 2-wire serial interface for in-system programming. 7. For operating voltage of 5V 10%, please refer to the 5V 10% AC and DC Characteristics.
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23. Packaging Information
23.1 8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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23.2
20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
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23.3 32A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM - - 1.00 9.00 7.00 9.00 7.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B
R
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2322G-CNFG-03/06
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2322G-CNFG-03/06

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